1. Field
The present invention relates to an automatic design method of a semiconductor integrated circuit, an automatic design system of a semiconductor integrated circuit, and a semiconductor integrated circuit.
2. Description of the Related Art
By a recent demand for a microfabrication, even if a mask taking a shape in accordance with a layout design is used, it is hard to form, on a wafer, a pattern in accordance with the design pattern. As means for enhancing a fidelity of a design, there have widely been utilized techniques referred to as an optical proximity correction (OPC) and a process proximity correction (PPC) which serve to create a mask pattern for forming, on a wafer, a pattern in accordance with a design value (The OPC and PPC will be hereinafter referred to as “OPC”).
A verification of the fidelity of the design is important for taking a countermeasure against a systematic defect which is generated due to each manufacturing step, and there is carried out a check based on a lithographic simulation as one of effective countermeasures (hereinafter referred to as a “lithographic rule check”). In the lithographic rule check, a simple lithographic simulation is executed for a pattern subjected to the OPC, and this obtained pattern is compared with a design pattern, thereby checking a shift. Consequently, a portion which might make troubles on a device basis is detected.
In recent years, in addition to a method of correcting a mask pattern, there has been proposed a technique referred to as a “target MDP processing” for correcting a target design pattern itself in accordance with a certain rule (for example, see JP-A 2005-24903 (KOKAI)). The target MDP processing serves for an easy formation on a wafer when it is predicted that specific pattern types are hard to form on the wafer, by correcting the target pattern types. The target MDP processing deforms a design pattern itself to form a pattern shape different from an original pattern shape on a wafer. Therefore, it is important that an upper limit of an amount of a correction is determined within a range causing no problem on a design basis, and the target MDP processing is used within the range.
On the other hand, a countermeasure to be taken against a random defect caused by dust stuck in a process for manufacturing a semiconductor integrated circuit has been increasingly important because of a recent microfabrication. At a step of carrying out a layout design for the semiconductor integrated circuit, various countermeasures have been started to be executed. For the countermeasures, the following is effective, that is:                (a) a contact and a via are multiplexed;        (b) a space between wirings is relieved;        (c) a wiring width is increased; and        (d) a redundant circuit is designed.By taking each of the countermeasures of (a) to (d), it is possible to expect a reduction in a via defect probability, a reduction in a short circuit defect generation probability between wirings, a reduction in an open defect generation probability of the wiring, and an enhancement in a yield by a defect generation relief in a memory portion.        
In an existing design apparatus, however, it is hard to implement the systematic defect countermeasure and the random defect countermeasure at the same time. For this reason, in a general design apparatus, the following phenomena are caused when the countermeasures of (b) and (c) are executed, for example.
(1) The processing of relieving a space between the wirings has an advantage that a design originating relationship of a cross talk can be improved and also has an advantage that the short circuit defect generation probability between the wirings can be reduced. However, a wiring length tends to be increased so that the open defect generation rate of the wiring is increased. For this reason, it is necessary to suppress an excessive increase in the wiring length, and furthermore, to increase the wiring width as a postprocessing.
(2) The processing of increasing the wiring width can be implemented by a target MDP processing through a lithographic margin viewpoint. In order to reduce the open defect generation probability of the wiring, however, it is necessary to further increase the amount of a correction by the target MDP processing. When the wiring length is increased the open defect generation probability of the wiring is increased. For this reason, it is also necessary to further increase the wiring width. However, when the amount of a correction is increased, a large number of steps are generated on the wiring pattern. As a result, the OPC cannot be processed properly so that troubles are generated in a wafer shape, and a yield is deteriorated. When generation probability of this yield deterioration caused by the above is increased, it is necessary to carry out a modifying work in a lithographic rule check for the wiring pattern extending in a large scale region. For this reason, a great deal of computer resources and processing time are required for the modification so that it is hard to carry out a verification in a practical time. At the same time, it is also impossible to disregard the influence of an increase in a wiring capacity on a circuit operation.